1. Field of Invention
The present invention relates to a stacked memory having a plurality of built-in memory chips, a memory module mounted with a plurality of stacked memories and a memory system having the memory module.
2. Description of the Related Art
An access time of a memory such as a DRAM has recently been sped up and with this, memory systems making use of a point-to-point bus and a daisy chain bus have come to be an object for consideration in order to ensure the waveform quality of signals transmitted at high speeds (cf., for example, RAMBUS Co. U.S.A., Yellowstone Memory System: Rich Warmke, “Yellowstone, A Next Generation memory Signaling Technology” RAMBUS DEVELOPER FORUM, OCT. 29, 2002, [Oct. 30, 2003, retrieved] internet <URL:    http:rambus.com/rdf/rdf2002/pdf/rdf_consumer_track.pdf.>)
More specifically, memory modules have been envisioned which use multibit point-to-point buses to transmit DQ (data) signals and DQS (DQ strobe) signals while using daisy chain buses to transmit control signals such as CA (command address) signals, CLK (clock) signals and CS (chip select) signals.
Presently, a single-rank memory configuration and a double-rank memory configuration are known with regard to a 64-bit I/O memory module. The single-rank memory configuration has eight 4-bit I/O (data width) memories mounted on each of the front and reverse surfaces of the module substrate, i.e., a total of sixteen memories, and activates all memories at the same time. The double-rank memory configuration has eight 8-bit I/O (data width) memories mounted on each of the front and reverse surfaces of the module substrate, i.e., a total of sixteen memories. In this memory configuration, memories mounted on each of the front and reverse surfaces of the module substrate share a DQ signal wiring of 8-bit width, and eight memories on either a front surface or a reverse surface are activated at the same time.
FIGS. 1A and 1B represent a conventional memory module of a 64-bit I/O, double-rank configuration.
Memory module 101 shown in FIGS. 1A and 1B has a structure in which eight memories (DRAMS) are mounted on each of the front and reverse surfaces of module substrate 102, totaling sixteen memories. Each memory 103 is of an 8-bit I/O type, and two memories 103 arranged in opposed positions on the front and reversed surfaces of module substrate 102 share an 8-bit DQ signal wiring.
A point-to-point bus is employed for a DQ signal wiring of memory module 101 illustrated in FIGS. 1A, 1B making point-to-point connections between memory controller 104 and respective memories 103 (DRAM) in memory module 101. The point-to-point bus is terminated by an ODT (On Die Terminator) provided in each memory 103, whereby the reflections of the DQ signal and DQS signal transmitted through the point-to-point bus are prevented.
Further, daisy chain buses are employed for CA and CLK signal wirings and the CS signal wirings to select memories to be activated, wherein the CA and CLK signal wirings are shared by all the memories 103 of memory modules 101 with the ends of the wirings terminated with terminators. For reference, each of the CS signal wirings is shared exclusively by the group of the memories prescribed to be activated at the same time (rank). Memories 103 mounted on memory module 101 shown FIGS. 1A and 1B are divided into two groups (ranks) each made up of eight memories 103 arranged on the front and reverse surfaces, respectively, of module substrate 102. In this double-rank configuration of memory module 101, a bank of eight memories 103 is made active at the same time (for example, memories shaded with slant lines in FIG. 1B).
Nevertheless, a problem has been known concerning a memory module that the speed-up of memory access generally entails an increase in power consumption, which in turn causes the temperature of a package to be raised and consequently the performance of a memory to be degraded.
In the above-described memory modules of single- and double-rank configurations, the double-rank configuration needs smaller power consumption than the single-rank configuration on account of the number of memories set in an active state at the same time, thereby enabling a temperature rise to be suppressed. For this reason, it might be preferred to configure a memory module such that the number of memories set in the active state at the same time is further decreased in order to further reduce the power consumption of the memory module. For example, a four-rank configuration can be intended in which eight 16-bit I/O memories are mounted on each of the front and reverse surfaces of the module substrate totaling sixteen memories and each of banks of four neighboring memories, arranged in opposite positions on the front and reverse surface of the module substrate, shares a 16-bit DQ signal wiring and is set in an active state at the same time.
FIGS. 2A and 2B illustrate a conventional 64-bit I/O memory module in a four-rank configuration through the use of ordinary memories.
Memory module 201 represented in FIGS. 2A and 2B is configured such that eight memories are mounted on each of the front and reverse surfaces of module substrate 202 totaling sixteen memories (DRAM) 203, just like memory module 101 shown in FIGS. 1A and 1B.
Memory module 201 has a configuration such that memories 203 are of a 16-bit I/O each, and arranged in opposed positions on the front and reverse surfaces of module substrate 202 and further, four neighboring memories 203 share a 16-bit DQ signal wiring.
Point-to-point buses are employed for DQ signal wirings of memory module 201 shown in FIGS. 2A and 2B, just like memory module 201 shown in FIGS. 1A and 2B and a memory controller (not shown) and each of memories 203 mounted on module substrate 202 are connected through the point-to-point connection. An ODT (On Die Terminator), provided in each of memories 203, terminates the point-to-point bus to prevent reflections of the DQ and DQS signals transmitted by the point-to-point bus.
Further, daisy chain buses are employed for CA, CLK signal wirings and CS signal wirings, as is the case with memory module 101 shown in FIGS. 1A and 1B, with the CA, CLK signal wirings being shared by all the memories 203 in memory module 201 and the wiring ends thereof terminated by terminators. In addition, each CS signal wiring is shared exclusively by the group (rank) of memories 203 to be set in an active state at the same time.
Memories 203 to be mounted on memory module 101 shown in FIGS. 2A and 2B are arranged in opposed positions on the front and reverse surfaces of module substrate 202, and divided into four groups of four neighboring memories each, wherein in this memory module 201 in four-rank configuration, four memories 203 are activated at the same time (memories shaded with slant lines in FIG. 2A). Consequently, the power consumption is decreased as compared with memory module 101 of double-rank configuration as shown in FIGS. 1A and 1B.
In the four-rank memory module shown in FIGS. 2A and 2B, each of the banks of four neighboring memories each arranged in opposed positions on the front and reverse surfaces of a module substrate shares sixteen DQ signal wirings. As a result, it is required to arrange eight DQ signal wirings between two memories mounted on the front and reverse surfaces across the module substrate and further to branch the wirings into two directions to connect the branched wirings to the neighboring memories.
However, memories are mounted on a module substrate nearly too closely to leave any room so that distances between wirings are short and also limitations are imposed on the wiring directions of the DQ signal wirings for memories. Consequently, the degree of wiring freedom of the DQ signal wiring markedly drops down, the wiring lengths connecting to two memories become asymmetric and significantly fluctuate, and cross-talk noise and ISI (intersignal interference) noise increase. Furthermore, the fluctuations in the arrival timings of signals increase, the qualities of waveforms of the DQ signals are degraded causing difficulty in a high-speed transmission through a bus.
In addition, it is required to receive CA and CS signals in the same timing, because in a memory module, these signals are processed in the same way. For this reason, it is desired to coordinate the transmission characteristics of the CA signal wiring and the CS signal wiring not to make a difference in the transmission speeds of the CS signal and the CA signal.